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Chips are manufactured on wafers, but wafer bare chips cannot be directly used as chips because the material of wafers is silicon,
which is very fragile and the circuits cannot be directly connected to external circuits. Therefore, we need to put a shell on it and then connect the circuits,this process is called packaging.
Packaging, that is, the casing of semiconductor integrated circuits, is an extremely crucial link in integrated circuit products.
It not only provides placement, fixation, sealing and protection for the chip, but also plays an important role in enhancing the thermal conductivity.
Furthermore, packaging serves as the connection link between the internal world of the chip and the external circuits. The contacts on the chip are connected to the pins of
the package housing through wires, and these pins are connected to other devices with the help of wires on the printed circuit board.
semiconductor chips from the influence of components. Because the chip must be isolated from the outside world to prevent impurities in the air from corroding the chip
circuit and causing a decline in electrical performance. On the other hand, the packaged chips are also more convenient for installation and transportation.
The quality of packaging technology also directly affects the performance of the chip itself and the design and manufacture of the PCB (printed circuit board) connected to it.
Therefore, packaging technology is essential for chips. It is of vital importance. Each chip must go through the "packaging" process to become a perfect semiconductor product.
DIP refers to dual in-line packaging technology, which is an integrated circuit chip that adopts dual in-line packaging. CPU chips in DIP packaging have two rows of pins
and need to be inserted into a chip socket with a DIP structure. Of course, they can also be directly inserted into a circuit board with the same number of solder holes and
geometric arrangement for soldering. For use on a base, they are easy to replace and the soldering difficulty is also very low. Only an electric soldering iron is needed for
soldering and assembly. Such as 51 single-chip microcomputers, AC-DC controllers, optocoupler operational amplifiers, etc. are all using this type of packaging.
SOP refers to small form Factor (SOP) packaging technology. In this packaging form, the pins need to be led out from both sides of the package, forming an "L" shape.
The typical feature of this type of packaging is that many pins are made around the packaged chip. The packaging operation is convenient, the reliability is relatively high,
and the soldering is also relatively easy. Common SOP-8 and other packages are widely used in various types of chips.
The SO type packaging later gave rise to various variants, which can be classified as: TOSP (Thin Small Form Factor Package), SSOP (Small Form Factor SOP),
VSOP (Very Small Form Factor Package), SOIC (Small Form Factor Integrated Circuit Package), etc.
QFP refers to Square Flat packaging technology. In this packaging technology, the distance between the pins of the chip is very small and the pins are very thin.
Chips using this packaging form must be soldered to the motherboard using SMD(Surface Mount Device Technology). Chips installed with SMD do not require drilling holes on the motherboard.
Generally, there are pre-designed solder joints for the corresponding pins on the motherboard surface. Align each pin of the chip with the corresponding solder joints,
and the chip can be soldered to the motherboard. This packaging form is generally used for large-scale or large-scale integrated circuits.
QFN refers to surface mount packaging technology. It is a leadless and square-shaped package with conductive pins for electrical connection on all four sides of the package.
The pin distances are generally 0.65mm, 0.5mm, 0.4mm, and 0.35mm. Since there are no pins on the outside of the package body, its mounting area and height are smaller than
those of QFN. The QFN package has no gull-wing-shaped leads, and the conductive path between the internal pins and the pads is short.
BGA stands for Ball Grid Array Packaging Technology. BGA packaging is an electronic component packaging technology. It refers to the packaging of electronic components in
a multi-layer spherical structure composed of metals and ceramics to provide better thermal conductivity and a smaller packaging size.
BGA packaging can offer more connection points, several times more than ordinary plug-in packaging, thus providing higher signal integrity and lower resistance.
BGA packaging can also offer higher power density and lower electromagnetic interference (EMI). BGA packaging technology is widely applied in multiple fields
such as computers, communications, and consumer electronics.
PGA refers to Pin Grid Array packaging technology. In this packaging technology, there are multiple square-shaped pins inside and outside the chip.
Each square-shaped pin is arranged at certain intervals around the chip. During installation, the chip is inserted into a dedicated PGA socket.
Because this package has outward-extending pins, it is generally installed by insertion rather than surface mounting.
Chip packaging technology has undergone multiple generations of updates, and its technical performance has continued to improve. Nowadays,
the ratio of chip area to packaging area is getting closer and closer, the applicable frequency is constantly increasing, and the temperature resistance
performance is significantly enhanced. Meanwhile, the number of pins has increased, the spacing has decreased, the package weight has been reduced,
the reliability has improved, and the use has become more convenient.
So far, semiconductor packaging technology can be divided into the following stages:
The traditional packaging stage (1960s-1990s)
DIP (Dual In-line Package) : In the early days, it was mainly packaged in metal or ceramic, and was mainly used in chips with low pin numbers, such as early microprocessors.
SOP (Small Form Factor Package) : It ADAPTS to the demands of consumer electronics by reducing the volume, but still relies on Wire Bonding technology.
QFP (Four-Pin Flat Package) : The pin density is increased, but it is still limited by the two-dimensional planar layout.
2. High-density packaging stage (2000s-2010s)
BGA (Ball Grid Array Package) : By replacing pins with solder balls, it enhances I/O density and heat dissipation capability, and has become the mainstream package form.
CSP (Chip Level Packaging) : The packaging size is close to the die size and is widely used in mobile devices.
Flip Chip (Flip-chip soldering) : Directly connect the chip to the substrate by using protrusions, shorten the signal path and improve performance by 69.
3. Advanced Packaging Stage (2010s to present)
2.5D/3D packaging: Through technologies such as through-silicon vias (TSV) and interposers, vertical stacking of chips is achieved, breaking through the limitations of the plane.
For example, HBM (High Bandwidth Memory) significantly increases the memory bandwidth by 69 through 3D stacking.
Fan-Out packaging: Rewiring is directly done on the wafer without the need for a substrate, reducing costs and enhancing integration, such as TSMC's InFO Technology 610.
Heterogeneous integration and Chiplet: Integrating chips with different process nodes (such as logic, memory, and RF) into a single package
and achieving modular design through standardized interfaces (such as UCIe). A typical case is AMD's EPYC processor 910.
1) Miniaturization and high integration: Heterogeneous integrated 2.5D/3D chip packaging can achieve multi-functional fusion, and multi-dimensional space stacking
can save space and reduce packaging size. The cancellation of micro-protrusions enables interconnection between chips without protrusions, significantly enhancing
the interface bonding strength and achieving ultra-fine pitch. This can greatly increase the number of channels and improve the signal transmission efficiency.
2) Combining high performance with low cost: Driven by the rising demand for AI, the demand for computing power has seen explosive growth.
The performance improvement space brought about by promoting Moore's Law is limited, and the cost has multiplied. The through-hole TSV structure with silicon material
as the intermediate layer can achieve ultra-high density interconnection, but the preparation process of the silicon through-hole structure is cumbersome and costly.
3) 3D integration and deepening of heterogeneous architectures
Vertical stacking technology: Achieves micron-level interconnection spacing through Cu-Cu hybrid bonding, enhancing bandwidth and energy efficiency.
For instance, the 3D stacking technology of Intel and TSMC has been applied to AI accelerators and HBM memory 69.
System-in-package (SiP) : Integrating non-silicon devices such as sensors and optoelectronic components to meet the multi-functional requirements
of the Internet of Things and autonomous driving 710.
With the continuous advancement of technology, semiconductor packaging technology has undergone a significant transformation from the 1D PCB level to advanced 3D
hybrid bonding at the wafer level. It has shifted from the traditional device-oriented approach to the system-oriented one, that is, it has further expanded on the basis of
traditional functions such as signal transmission, support carriers, heat conduction, and chip protection in packaging. The signal transmission circuits of the system and
most active and passive components are integrated by using thin film, thick film processes and embedding processes, and combined with the high-density packaging of
chips and the external mounting process of components, thereby achieving the packaging integration of the system and reaching the highest density packaging.
This transformation has brought about significant improvements in four key parameters: power, performance, area and cost. To achieve more efficient, higher-bandwidth,
smaller-sized and lower-cost semiconductor packaging, 2.5D and 3D packaging technologies have emerged, integrating various advanced packaging processes.
Among them, the 2.5D packaging includes interlayers of different materials such as silicon-based, organic-based and glass-based interlayers;
While 3D packaging achieves smaller spacing dimensions and higher performance through micro-pump technology and hybrid bonding
technologies (such as direct connection of Cu-Cu). The development of these technologies marks a significant advancement in the field of semiconductor packaging,
laying a solid foundation for future applications in high-performance computing and other areas.
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